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EL7535
Data Sheet July 13, 2006 FN7003.5
Monolithic 350mA Step-Down Regulator
The EL7535 is a synchronous, integrated FET 350mA stepdown regulator in a MSOP10 package. The regulator is internally compensated, which makes it possible to use just five tiny external components to form a complete DC/DC converter. The regulator operates with an input voltage range from 2.5V to 6V, which accommodates supplies of 3.3V, 5V, or a Li-Ion battery source. The output can be externally set from 0.8V to VIN with a resistive divider. The EL7535 features PWM mode control. The operating frequency is typically 1.4MHz. Additional features include <1A shut-down current, short-circuit protection, and overtemperature protection. The EL7535 is available in the 10 Ld MSOP package and is specified for operation over the full -40C to +85C temperature range.
Features
* Extremely small 350mA DC/DC converter * Max height 1.1mm MSOP10 package * Possibly uses only five tiny external components with fixed output * Power-On-Reset output (POR) * Internally-compensated voltage mode controller * Up to 94% efficiency * <1A shut-down current * Overcurrent and over-temperature protection * Pb-free plus anneal available (RoHS compliant)
Applications
* PDA and pocket PC computers * Bar code readers
Ordering Information
PART NUMBER PART TAPE & (BRAND) MARKING REEL EL7535IY EL7535IY-T7 EL7535IY-T13 EL7535IYZ (Note) EL7535IYZ-T7 (Note) a a a BAACA BAACA 7" 13" 7" 13" PACKAGE 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) 10 Ld MSOP (Pb-free) PKG. DWG. # MDP0043 MDP0043 MDP0043 MDP0043 MDP0043 MDP0043
* Cellular phones * Portable test equipment * Li-Ion battery powered devices * Small form factor (SFP) modules
Typical Application Diagram
EL7535 (10 LD MSOP) TOP VIEW
VS (2.5V to 5.5V) VIN R3 100 C2 10F C3 0.1F R5 100k POR EN FB R2* 100k VO R4 100k R6 100k VDD
EL7535
EL7535IYZ-T13 BAACA (Note)
LX
L1 1.8H C1 10F
VO
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
R1* 124k
C4 470pF
Pinout
EL7535 (10 LD MSOP) TOP VIEW
1 SGND 2 PGND 3 LX 4 VIN 5 VDD FB 10 VO 9 POR 8 EN 7 RSI 6
RSI
PGND SGND
(1.8V @ 350mA)
* VO = 0.8V * (1 + R1 / R2)
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004, 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7535
Absolute Maximum Ratings (TA = 25C)
VIN, VDD, POR to SGND . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V LX to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) RSI, EN, VO, FB to SGND . . . . . . . . . . . . . . . -0.3V to (VIN + +0.3V) PGND to SGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500mA Operating Ambient Temperature . . . . . . . . . . . . . . . .-40C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER DC CHARACTERISTICS VFB IFB VIN, VDD VIN,OFF VIN,ON IDD
VDD = VIN = VEN = 3.3V, C1 = C2 = 10F, L = 1.8H, VO = 1.8V, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Feedback Input Voltage Feedback Input Current Input Voltage Minimum Voltage for Shutdown Maximum Voltage for Startup Supply Current VIN falling VIN rising PWM, VIN = VDD = 5V EN = 0, VIN = VDD = 5V
790
800
810 250
mV nA V V V A A m m A C C
2.5 2 2.2 400 0.1 70 45 1.5 T rising T falling VEN, VRSI = 0V and 3.3V VDD = 3.3V VDD = 3.3V VFB rising VFB falling ISINK = 5mA 86 35 0.8 -1 145 130
6 2.2 2.4 500 1 100 75
RDS(ON)-PMOS
PMOS FET Resistance
VDD = 5V, wafer test only VDD = 5V, wafer test only
RDS(ON)-NMOS NMOS FET Resistance ILMAX TOT,OFF TOT,ON IEN, IRSI VEN1, VRSI1 VEN2, VRSI2 VPOR Current Limit Over-temperature Threshold Over-temperature Hysteresis EN, RSI Current EN, RSI Rising Threshold EN, RSI Falling Threshold Minimum VFB for POR, WRT Targeted VFB Value POR Voltage Drop
1 2.4
A V V
95
% %
VOLPOR
70
mV
AC CHARACTERISTICS FPWM tRSI tSS tPOR PWM Switching Frequency Minimum RSI Pulse Width Soft-start Time Power On Reset Delay Time 80 Guaranteed by design 1.25 1.4 25 650 100 120 1.55 50 MHz ns s ms
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FN7003.5 July 13, 2006
EL7535 Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 PIN NAME SGND PGND LX VIN VDD RSI EN POR VO FB Negative supply for the controller stage Negative supply for the power stage Inductor drive pin; high current digital output with average voltage equal to the regulator output voltage Positive supply for the power stage Power supply for the controller stage Resets POR timer Enable Power on reset open drain output Output voltage sense Voltage feedback input; connected to an external resistor divider between VO and SGND for variable output PIN FUNCTION
Timing Diagram
VO MIN 25ns RSI
100ms POR
100ms
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FN7003.5 July 13, 2006
EL7535 Block Diagram
VDD VO 10pF 124K FB 5M + PWM COMPENSATION + CURRENT LIMIT + PWM COMPARATOR CONTROL LOGIC
VIN
100K CLOCK 1.4MHz EN EN SOFTSTART RAMP GENERATOR
P-DRIVER LX 1.8 1.8V 350mA
10F
N-DRIVER UNDERVOLTAGE LOCKOUT TEMPERATURE SENSE
10F
5V
+ -
BANDGAP REFERENCE SGND
PGND 100K POR PG
RSI
POR
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FN7003.5 July 13, 2006
EL7535 Typical Performance Curves
100 95 90 EFFICIENCY (%) 85 80 75 70 65 60 0 100 200 IO (mA) 300 400 VO=1.2V VO=1.8V VO=2.5V EFFICIENCY (%) 100 VO=3.3V 95 90 85 80 75 70 65 60 0 100 200 IO (mA) 300 400 VO=1V VO=1.8V VO=1.2V
VIN=5V
VIN=3.3V
VO=2.5V
FIGURE 1. EFFICIENCY
FIGURE 2. EFFICIENCY
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
0 P1 /W C SO M 115 = A J
ALLOWABLE POWER DISSIPATION (W)
0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
M SO
JA
P =2 06 10 C /W
FIGURE 3. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 4. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Waveforms
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 350mA with component values shown on page 1, unless otherwise noted
VIN (2V/DIV)
VIN (1V/DIV) IIN (0.2A/DIV) VO (1V/DIV)
ALLOWABLE POWER DISSIPATION (W)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
VO (2V/DIV) POR (2V/DIV)
0.5ms/DIV
50ms/DIV
FIGURE 5. START-UP 1
FIGURE 6. START-UP 2
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FN7003.5 July 13, 2006
EL7535 Waveforms
(Continued)
All waveforms are taken at VIN = 3.3V, VO = 1.8V, IO = 350mA with component values shown on page 1, unless otherwise noted
VIN (2V/DIV) VO (2V/DIV) IO RSI (2V/DIV) POR (2V/DIV) 350mA 100mA
VO
20mV/DIV
50ms/DIV
0.2ms/DIV
FIGURE 7. POR FUNCTION
FIGURE 8. TRANSIENT RESPONSE
VIN
100mV/DIV
iL
0.5A/DIV
VLX
2V/DIV
VO 1s/DIV
10mV/DIV
FIGURE 9. STEADY-STATE
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FN7003.5 July 13, 2006
EL7535 Applications Information
Product Description
The EL7535 is a synchronous, integrated FET 350mA stepdown regulator which operates from an input of 2.5V to 6V. The output voltage is user-adjustable with a pair of external resistors. The internally-compensated controller makes it possible to use only two ceramic capacitors and one inductor to form a complete, very small footprint 350mA DC/DC converter. The POR output also serves as a 100ms delayed Power Good signal when the pull-up resister R4 is installed. The RSI pin needs to be directly (or indirectly through a resister R6) connected to Ground for this to function properly.
Output Voltage Selection
Users can set the output voltage of the converter with a resister divider, which can be chosen based on the following formula:
R 2 V O = 0.8 x 1 + ------ R 1
PWM Operation
In the PWM mode, the P channel MOSFET and N channel MOSFET always operate complementary. When the PMOSFET is on and the NMOSFET off, the inductor current increases linearly. The input energy is transferred to the output and also stored in the inductor. When the P channel MOSFET is off and the N channel MOSFET on, the inductor current decreases linearly, and energy is transferred from the inductor to the output. Hence, the average current through the inductor is the output current. Since the inductor and the output capacitor act as a low pass filter, the duty cycle ratio is approximately equal to VO divided by VIN. The output LC filter has a second order effect. To maintain the stability of the converter, the overall controller must be compensated. This is done with the fixed internally compensated error amplifier and the PWM compensator. Because the compensations are fixed, the values of input and output capacitors are 10F to 22F ceramic. The inductor is nominally 1.8H, though 1.5A to 2.2H can be used.
Component Selection
Because of the fixed internal compensation, the component choice is relatively narrow. For a regulator with fixed output voltage, only two capacitors and one inductor are required. We recommend 10F to 22F multi-layer ceramic capacitors with X5R or X7R rating for both the input and output capacitors, and 1.5H to 2.2H inductance for the inductor. The RMS current present at the input capacitor is decided by the following formula:
V IN x ( V IN - V O ) I INRMS = ------------------------------------------------ x I O V IN
This is about half of the output current IO for all the VO. This input capacitor must be able to handle this current. The inductor peak-to-peak ripple current is given as:
( V IN - V O ) x V O I IL = ------------------------------------------L x V IN x f S
Start-Up and Shut-Down
When the EN pin is tied to VIN, and VIN reaches approximately 2.4V, the regulator begins to switch. The output voltage is gradually increased to ensure proper softstart operation. When the EN pin is connected to a logic low, the EL7535 is in the shut-down mode. All the control circuitry and both MOSFETs are off, and VOUT falls to zero. In this mode, the total input current is less than 1A. When the EN reaches logic HI, the regulator repeats the start-up procedure, including the soft-start function.
* L is the inductance * fS the switching frequency (nominally 1.4MHz) The inductor must be able to handle IO for the RMS load current, and to assure that the inductor is reliable, it must handle the 1.5A surge current that can occur during a current limit condition. In addition to decoupling capacitors and inductor value, it is important to properly size the phase-lead capacitor C4 (Refer to the Typical Application Diagram). The phase-lead capacitor creates additional phase margin in the control loop by generating a zero and a pole in the transfer function. As a general rule of thumb, C4 should be sized to start the phaselead at a frequency of ~2.5kHz. The zero will always appear at lower frequency than the pole and follow the equation below:
1 f Z = ---------------------2R 2 C 4
RSI/POR Function
When powering up, the open-collector Power-On-Reset output holds low for about 100ms after VO reaches the preset voltage. When the active-HI reset signal RSI is issued, POR goes to low immediately and holds for the same period of time after RSI comes back to LOW. The output voltage is unaffected. (Please refer to the timing diagram). When the function is not used, connect RSI to ground and leave open the pull-up resister R4 at POR pin.
Over a normal range of R2 (~10-100k), C4 will range from ~470-4700pF. The pole frequency cannot be set once the zero frequency is chosen as it is dictated by the ratio of R1 and R2, which is solely determined by the desired output set
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FN7003.5 July 13, 2006
EL7535
point. The equation below shows the pole frequency relationship:
1 f P = --------------------------------------2 ( R 1 R 2 )C 4
Layout Considerations
The layout is very important for the converter to function properly. The following PC layout guidelines should be followed: * Separate the Power Ground ( ) and Signal Ground ( ); connect them only at one point right at the pins * Place the input capacitor as close to VIN and PGND pins as possible * Make the following PC traces as small as possible: - from LX pin to L - from CO to PGND * If used, connect the trace from the FB pin to R1 and R2 as close as possible * Maximize the copper area around the PGND pin * Place several via holes under the chip to additional ground plane to improve heat dissipation The demo board is a good example of layout based on this outline. Please refer to the EL7535 Application Brief.
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a short-circuit occurs in the load, the preset current limit restricts the amount of current available to the output, which causes the output voltage to drop below the preset voltage. In the meantime, the excessive current heats up the regulator until it reaches the thermal shut-down point.
Thermal Shut-Down
Once the junction reaches about 145C, the regulator shuts down. Both the P channel and the N channel MOSFETs turn off. The output voltage will drop to zero. With the output MOSFETs turned off, the regulator will soon cool down. Once the junction temperature drops to about 130C, the regulator will restart again in the same manner as EN pin connects to logic HI.
Thermal Performance
The EL7535 is in a fused-lead MSOP10 package. Compared with regular MSOP10 package, the fused-lead package provides lower thermal resistance. The JA is 100C/W on a 4-layer board and 125C/W on 2-layer board. Maximizing the copper area around the pins will further improve the thermal performance.
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FN7003.5 July 13, 2006
EL7535 Mini SO Package Family (MSOP)
0.25 M C A B D N A (N/2)+1
MDP0043
MINI SO PACKAGE FAMILY SYMBOL A A1 A2 MSOP8 1.10 0.10 0.86 0.33 0.18 3.00 4.90 3.00 0.65 0.55 0.95 8 MSOP10 1.10 0.10 0.86 0.23 0.18 3.00 4.90 3.00 0.50 0.55 0.95 10 TOLERANCE Max. 0.05 0.09 +0.07/-0.08 0.05 0.10 0.15 0.10 Basic 0.15 Basic Reference NOTES 1, 3 2, 3 Rev. C 6/99
E
E1
PIN #1 I.D.
b c D
B
1 (N/2)
E E1 e
e C SEATING PLANE 0.10 C N LEADS b
H
L L1 N
0.08 M C A B
NOTES: 1. Plastic or metal protrusions of 0.15mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H".
L1 A c SEE DETAIL "X"
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
A2 GAUGE PLANE L DETAIL X
0.25
A1
3 3
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN7003.5 July 13, 2006

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